[Computer Structure] 기말 강의 내용 정리 pdf

내 모든 필기 테크닉이 담긴 정수라고 볼 수 있는 컴퓨터 구조 수업 기말고사 pdf 정리 자료.

앞으로 이렇게까지 할 일이 있을까 싶다.

적어도 내가 A+을 확신하는 과목 중에 한 번도 A+을 놓친 적은 없었으니, 이것도 A+ 강의 자료가 될 것이다.

아직 기말고사 끝나지도 않았지만 ㅋㅋ

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Processor Implementation for MIPS

Introduction
- CPU Performance Factors
Logic Design Basics
- Information Encoded In Bynary
- Combinational Element
- State(Sequential) Element
Simple Instruction Execution Step
- Program Counter
- Register Number
- Instruction Class
Abstract Implementation View
- Assumption
- Clocking Methodologies
- Data path & Control
Processor Design
- Fetch
- Decode
- Execute R Format
- Execute Load&Store
- Execute Branch
- Execute Jump
Simple Datapath
- Fetch, R, and Memory Access Portion
- Multiplexor Insertion
- MUX for Branch
- Clock Distribution
- ALU Control
- Control Unit
ALU Control
- Truth table
Single Cycle
- Instruction Critical Path
- Advantage & Disadvantage
Pipeline
- Concept
- Five Stage
- MIPS pipeline
MIPS Pipelien Datapath (+Mods)
- State Register
- Register Category
- As-is
- To-be
- Control Unit of Pipeline
Multicycle
- Overview
- Simple Graphically Representing

Pipeline Hazard

Exploating Memory Hierarchy

Basic Structure
- Memory Hierarchy
Memory & Storage
- DRAM Memory Latency & Bandwidth
- Magnetic Disk Storage
- Flash Storage
- Flash Type
- Flash Memory Characteristic
- SDD vs HDD
SDD
- Leveling Architecture
- Level Policies
- Erase Before Write
- Out Place Update
- Address Mapping
Garbage Collector
- Concept
- Minimum Write Overhead
- Maximum Free Page
- Page Access Patterns
FTL
- Why Use FTL
- Implementation
Cell Level
- SLC, MLC, TLC
Locality
- Memory Wall
- Principle
- Advantage
Memory Hierarchy
- Two Major Memory Performance Metrics
- Technologies
- Terminology
- Characteristics

Cache & Memory System

Cache Basic
- How Managed?
- Two Main Perspective
Direct Mapped Cache
- Concept
- MIPS Direct Mapped Cache
- Intrinsity FastMATH
- Advantage of Spatial Locality
Evaluate
- Miss Rate vs. Block Size vs. Cache Size
- Block Size
- Cache Field Size
Cache Hits
- Handling
Cache Misses
- Source
- Read Misses (Single Word Block)
- Write Misses (Single Word Block)
- Combination
- Read Misses (Multi Word Block)
- Write Misses (Multi Word Block)
System Bus
- Type
- One Word Wide Bus, One Word Block
- One Word Wide Bus, Four Word Block
- Four Word Wide Bus, Four Word Block
- Interleaved Memory, One Word Wide Bus
Cache Performance
- Measuring
- Impacts
- Average Memory Access Time (AMAT)
Miss Rate
- Associative
- Two-way Associative
- Four-way Associative
- Direct vs. Set Associative Comparsion
- Cost of Set Associative
- Befit of Set Associative
Block Size
- Trade-off
- Effects in Multi-Core
Miss Penalty
- Multi Level Cache
- Design Consideration
Summary
- Improving Cache Performance

Memory & Storage

Virtual Memory
- Concept
- Sharing Physical Memory
- Address Translation
- Virtual Addressing with Cache
Translation Lookaside Buffers(TLBs)
- Concept
- TLB & Cache Interaction
- Event Combinations
Advanced
- Why not a Virtually Addressed Cache?
- Synonym Problem
- Homonym Problem
Summary
- Cache
- Main Memory